MultiMIPS 8051 Operating System Kernel

Personal Considerations

Design Philosophy

The Five Levels

8051 Hardware Resource Usage

Personal Considerations

The motivation for constructing this Kernel is threefold. First, I want to learn

the 8051 chip architecture, and I can imagine no better way than to construct

interesting to see now how the design principles have held up over

approximately 30 years. [Actually, the time difference is only 10 years; my

thesis work was completed by about 1970, and the design of the 8051

processor was completed by about 1980.]

One thing to note here is my belief and contention that over the course of

these past three decades, computers have not changed other than to become

merely smaller, faster, and cheaper. The essential elements are the same:

CPU, registers, memory for program and data storage, interrupt system,

external storage, and so on. And the principles of software design have not

changed; structured programming has evolved into OOP, but the principles

concrete, and the relationships among these units. The expression computer

software structure refers to the functional units [functions, subroutines,

coroutines, objects, etc] of the software, and the communication techniques

by which internal information flows among them. [Internal information

refers to program control variables and context dependent information, as

opposed to external information which is data being processed by the

program.] It is the internal information flows that bind the program units

together and impart to the system its structure.

In considering system structure, we must also consider the structure of the

individual software units. These units should be constructed according to the

abstraction of the next lower level machine. A hierarchical structure results

because of the communication techniques within levels and between

adjacent levels. It is not too soon to note that it is a violation of design

principle that communication would skip a level. So the above compound

phrase within levels and between adjacent levels is precise

The Five Levels

Level-0 is the hardware machine. The purpose of the higher levels is to

abstract from this machine to one that more readily lends itself to building

the next higher level, and eventually to interfacing to user programs. The

master design criterion for the lower levels is efficient access to the

no other processes should be executed here. In particular, as a general

principle, software at this level should not make decisions, but rather should

only execute predetermined processes.

Level-2 software initializes variables in the level-1 machine to prepare the

latter to process information transfers in response to interrupts. Specifically,

these variables include buffer pointers, the item count and memory address

for information transfers, and the [optional] memory address of a process,

designated by a next higher level routine, to be executed as an extension of

the interrupt service routine. Level-2 should set up level-1 so that the latter

can operate, as much as possible, in a predetermined way when the interrupt

occurs.

Level-3 software is utility programs and user programs. The main utility

program at this level is the command interpreter. This program inputs text,

in addition to the keyboard.

Level-4. One view of level-4 is that, for machines with external mass

storage [hard drives, etc], it provides automatic access to level-3 programs

that are stored on the mass storage device. For a microcontroller these

programs may be stored in external memory devices. These programs can be

accessed by using the system command interpreter either from the keyboard

or from other running programs. This can provide a very powerful operating

system kernel.

8051 Hardware Resource Usage

purpose flag PSW.5 [F0].

Program Memory

The Kernel occupies less than 0x300 bytes of program memory. Using the

MultiMIPS HEX file relocator program, the Kernel can be placed virtually

anywhere in the program memory space.

SFR Memory

The Kernel ISRs [interrupt service routines or interrupt handlers] preserve

the contents of any SFRs used, except for SFRs specific to devices that it is

using itself. The Level-2 routine used to output individual data bytes to the

serial port preserves the SFRs that it uses.

Register Banks 0-3

The Kernel ISRs preserve the contents of any registers that it uses.

Indirect Address Area

The Kernel uses Indirect Address Area memory beginning immediately after

it's scratch pad memory:

routine: 1 byte; command interpreter: 4 bytes. These are needed

simultaneously.

first instruction of the Kernel to be executed on reset or restart.

be]. It should be similar to: 758148

4. 75 is a MOV instruction; 81 is the stack pointer SFR; 48 is the

IDATA memory address for the stack.

5. Change the [48] to whatever you wish between the current value and

the end of the IDATA memory area [0xFF].

External Data Memory

The Kernel uses no external data memory.

Parallel I/O Ports

processor is 20 MHz].

Interrupts

…..